1. Field of the Invention
The invention relates in a general way to random access memories, and in particular to the structure of high-speed random access memory cells.
2. Description of the Related Art
The publication The Techniques of the Engineer describes in article E 2432 on page 24 an example of a 6-transistor SRAM memory cell. This memory cell includes a flip-flop. This flip-flop, as shown in FIG. 5, consists of two storage nodes and has read-write terminals Q and Q. Each storage node consists of an nMos transistor and a pMos transistor. The nMos transistors are driver transistors Tcom1 and Tcom2 and the pMos transistors are load transistors Tc1 and Tc2. The terminals Q and Q of the flip-flop are connected to a 1-bit line and to a 0-bit line respectively through respective switching transistors. The gates of these switching transistors are connected to one and the same word selection line. These transistors act as a read-write switch in the flip-flop.
In order to obtain sufficiently high read-write speeds, driver transistors are used that have a substantial gate width. In order for the cell to have sufficient stability, the width of the gate of the switching transistors must be increased proportionately to the width of the gate of the driver transistors. Thus, a cell of this kind requires a significant substrate surface area in order to be both high-speed and stable. Moreover, the width of gate used makes it necessary to equip the circuit with a read signal amplifier so as to obtain a sufficient read current. A matrix using such cells additionally requires significant multiplexing means.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.